Career

Design for Test (DFT) Engineers

• Experience: 3–6 years

• Must-Have:

  • Hands-on experience with scan insertion, ATPG, MBIST, and boundary scan (JTAG)

  • Exposure to tools like Tessent, Synopsys DFT Compiler, or SpyGlass

  • Experience working on SoCs for high-performance computing or mobile

• Preferred: Background with Intel DFT flows or similar

Physical Design (PD) Engineers

• Experience: 4–6 years

• Must-Have:

  • Experience with floorplanning, placement, CTS, routing, STA, and physical verification

  • Tools: Cadence Innovus, Synopsys ICC2, PrimeTime, RedHawk

  • One or more successful tapeouts, preferably with AMD or other top-tier clients

• Preferred: Familiarity with 7nm or below technology nodes